1. Field of the Invention
The present invention relates to a single flux quantum circuit, and more particularly to a method for implementing sigma-delta modulation, or delta modulation, for converting an analog signal into a digital signal.
2. Description of the Related Art
SFQ (Single Flux Quantum) circuits handle a single flux quantum (F0=h/2e=2.07×10−15 Weber) as an information carrier. These single flux quantum circuits are superconducting circuits that are characterized by ultrahigh-speed operation whose speed is the order of several tens of gigahertz (109 Hz) or higher, and low-power property whose level is several microwatts (μW) per gate or lower. On the basis of the principles shown in IEEE Transaction on Applied Superconductivity, Vol. 1, No. 1 (1991) p. 3 (nonpatent literature 1), various kinds of logic gates were developed in the past, and circuits for practical use, in which these logic gates are used in combination, are widely being developed.
The SFQ circuits are applied to A/D (Analog/Digital) converters. In this case, in order to make full use of high speed that is an advantage of the SFQ circuit, an over-sampling method is adopted as a conversion method. To be more specific, an analog signal is sampled/quantized with a frequency that is sufficiently higher than a frequency band (the bandwidth), and with the accuracy of a few bits (this processing is called “oversampling”). Next, the quantized data signal is subjected to signal processing by a decimation filter. As a result, a digital signal with high accuracy is acquired in the required bandwidth. At the time of the quantization, quantization noise which occurs spread out to a band whose frequency is one half a sampling frequency. In addition to it, the quantization noise does not depend on the sampling frequency. Therefore, with the increase in sampling frequency, noise included in the bandwidth of the analog signal can be made smaller. Because of it, by improving a ratio of the sampling frequency to the bandwidth of the input signal (over-sampling ratio), it is possible to increase the conversion accuracy (the bit accuracy). For example, by improving the over-sampling ratio by twice, the bit accuracy is increased by 0.5 bit.
U.S. Pat. No. 5,140,324 (patent document 1) and IEEE Transaction on Applied Superconductivity, vol. 3 (1993) p. 2732 (nonpatent literature 2) disclose a case where an oversampling method based on a SFQ circuit is the sigma-delta modulation. In addition, IEEE Transaction on Applied Superconductivity, vol. 5 (1995) p. 2260 (nonpatent literature 3) discloses a case where an oversampling method is the delta modulation. Principles of how the conventional sigma-delta and delta modulator circuits operate will be described along these papers.
FIG. 1A is a block diagram illustrating the principles and configuration of a sigma-delta modulator; and FIG. 1B is a block diagram illustrating the principles and configuration of a delta modulator.
A sigma-delta modulator 100 includes an adder circuit 101, an integration circuit 102, a comparator circuit 103, and a one-bit D/A conversion circuit 104. First of all, an analog signal 111 is integrated by the integration circuit 102, and is then inputted into the comparator circuit 103. The result of the comparison is output as a quantized data signal 112 that is a digital signal whose value is “1” or “0”. In addition, the result of the comparison is converted into an analog signal by the D/A conversion circuit 104. The analog signal is then fed back to the input side of the integration circuit 102 by the adder circuit 101. As the quantization data signal output that is obtained from the comparator circuit 103, “1” is output. The density of the output “1” is proportional to a signal level of the input signal 111. By calculating this density using a digital filter that is placed in the subsequent stage of the modulator circuit, a digital signal on which the input signal is reflected is acquired.
On the other hand, because the delta modulator does not have an integration circuit in the preceding step of the comparator circuit 103, the analog signal 111 is not subjected to the integration processing. Only a feedback signal received from the comparator circuit 103 is integrated by the integration circuit 102. Because of it, only a change in the analog signal 111 is reflected on the digital signal that is output from the comparator circuit 103. In order to restore from the output signal the digital signal on which the analog signal is reflected, it is necessary to place a digital integrator 105 between the modulator and a digital filter.
These methods have characteristics that the frequency distribution of quantization noise occurring in an A/D conversion process is moved to a frequency band whose frequency is higher than the signal bandwidth to reduce quantization noise within the signal bandwidth. This method for changing the frequency distribution of noise is called “noise shaping”. By use of this noise shaping, it is possible to improve the bit accuracy of oversampling more efficiently. For example, by improving an over-sampling ratio by twice, the effect of the noise shaping causes the bit accuracy to increase by 1.0 bits. If the effect of the oversampling described above is included, the bit accuracy increases by 1.5 bits. For this reason, by forming a modulator using the SFQ circuit that is capable of high-speed operation whose speed is the order of several tens of gigahertz, the over-sampling ratio is improved by 10 through 100 times as compared with a case where a modulator circuit is formed by a semiconductor circuit. Accordingly, it is possible to expect a dramatic improvement in bit accuracy.
FIG. 2A is a diagram illustrating as an example an equivalent circuit of a sigma-delta modulator 200 based on the SFQ circuit. The circuit includes: an integration circuit 203 that is constituted of an integration resistor 201 and an integrating inductor 202; and a comparator 206 that is constituted of two Josephson junctions 204, 205. First of all, an inputted analog signal 210 is integrated by the integration circuit 203. The result of the integration appears as a circular current 211 flowing through the integrating inductor 202. This circular current 211 is inputted into the comparator 206. As a result of inputting a SFQ clock signal 212 that is used as a sampling signal, the circular current 211 is compared with a threshold value specific to the comparator 206. The result of the comparison is then output as a SFQ data signal 213. The comparator 206 feeds back this result to the integration circuit 203. Incidentally, besides the analog signal 210, an offset current is inputted into the integration circuit 203 from an offset current source 207.
Here, how the comparator 206 operates will be described. The circular current 211 of the integration circuit 203, which is a current to be compared, is branched into two: one flows through the Josephson junction 204, and the other flows through the Josephson junction 205. If the SFQ clock signal 212 is inputted into the comparator 206 with the above state being kept unchanged, a new circular current 214 caused by the SFQ clock signal flows through the Josephson junctions 204, 205. In this case, the circular current 211 from the integration circuit 203 and the circular current 214 caused by the SFQ clock signal 212 flow through the Josephson junction 205 in the same direction. On the other hand, the circular current 211 and the circular current 214 flow through the Josephson junction 204 in directions that are opposite to each other.
If the circular current 211 of the integration circuit 203 exceeds a threshold value of the comparator 206, a value obtained by totaling the circular current 214 caused by the SFQ clock signal 212 flowing through the Josephson junction 205 and the circular current 211 of the integration circuit 203 exceeds a critical current value of the Josephson junction 205. Therefore, the Josephson junction 205 enters a voltage state for a few picoseconds, which causes a voltage pulse to occur at an output terminal of the comparator 206 for a few picoseconds. As a result, one SFQ is output from the sigma-delta modulator 200 as the quantized data signal 213. This means that a digital signal “1” has been output. Hereinafter, a series of operation relating to this Josephson junction is expressed as “a Josephson junction switches”. In addition, when the Josephson junction 205 switches, a circular current which is equivalent to one SFQ also flows on the side of the integration circuit 203 in a direction that is opposite to the circular current 211 of the integration circuit which originally flows. This means that a circular current which is equivalent to one SFQ has been fed back from the comparator 206 to the integration circuit 203 side.
On the other hand, if the circular current 211 of the integration circuit 203 does not exceed a threshold value of the comparator 206, then a value obtained by totaling the circular current 214 caused by the SFQ clock signal 212 flowing through the Josephson junction 204 and the circular current 211 of the integration circuit 203 exceeds a critical current value of the Josephson junction 204. Accordingly, the Josephson junction 204 switches this time, which does not cause a voltage pulse to occur at the output terminal of the comparator 206. As a result, no SFQ is output from the comparator 206. This means that a digital signal “0” has been output from the sigma-delta modulator 200 as the quantized data signal 213. Moreover, in this case, the feedback from the comparator 206 to the integration circuit 203 also does not occur. On the basis of the principles of operation described above, integration, comparison, and feedback, which are required for the sigma-delta modulation, are achieved.
Besides the analog signal 210, an offset current is inputted from the offset current source 207 into the integration circuit 203. In general, a value of this electric current is set at 50% of the input full scale of the analog signal 210. This electric current controls the operation of the comparator when no signal is inputted as the analog signal 210. To be more specific, when no signal is inputted as the analog signal 210, a state in which “1” and “0” are alternately output is created in response to the input of the sampling clock signal (the SFQ clock signal 212). Then, the pulse density of “1” included in a digital data signal, which is output from the modulator, is set at 50%.
The delta modulation can also be explained on the basis of the principles that are substantially the same as those of the sigma-delta modulation. FIG. 2B is a diagram illustrating as an example an equivalent circuit of a delta modulator 220 based on the SFQ circuit. The circuit is substantially the same as that of the sigma-delta modulation shown in FIG. 2A. A point of difference between these circuits is that instead of directly inputting the analog signal 210 into the integration circuit 203, the analog signal 210 is inputted from the input inductor 208 that is magnetically coupled to the integrating inductor 202 of the integration circuit 203. The analog signal 210 is not subjected to the integration processing. Only a feedback signal from the comparator 206 is integrated. Because of it, only a change in the analog signal is reflected on the SFQ quantized data signal 213 that is output from the comparator 206. In order to restore from the output signal the digital signal on which the analog signal is reflected, it is necessary to place a digital integrator on the output side of the modulator.
These modulator circuits based on the SFQ circuit can be very easily implemented because the modulator circuits can be formed by a resistor, one or two inductors, and two or four Josephson junctions that are required to constitute a comparator. In addition, a SFQ signal required for the circuit operation is only the sampling clock signals. Accordingly, the SFQ signal is not restricted by the timing between two or more SFQ signals in the circuit, which is in general a problem of the SFQ circuit. For this reason, it is possible to expect that these modulator circuits achieve the highest speed operation in principles.
Regardless of whether it is a semiconductor circuit or a SFQ circuit, when an A/D converter is used, great importance is placed on the conversion accuracy thereof. As described above, in the case of the sigma-delta modulation and the delta modulation, by using noise shaping with high ratio of a sampling frequency to the frequency band of the input signal (over-sampling ratio), an efficient improvement in the conversion accuracy has been achieved.
However, because of the two causes described below, the actually acquired bit accuracy of a modulator, which is formed of a SFQ circuit, is lower than a theoretical value.
First of all, the first cause is thermal noise that occur in Josephson junctions constituting a comparator, and that occur in a resistor constituting part of an integration circuit. Basically, a Josephson junction includes a resistance component in a voltage state. Moreover, when a Josephson junction included in the SFQ circuit switches, a shunt resistor is connected to the Josephson junction to keep a voltage state unchanged for a few picoseconds. On the assumption that the resistance component is R, a root mean square of the current amplitude i of thermal noise occurring at both ends of the junction is expressed by Equation (1) as follows:
                              i          2                =                              4            ⁢                          k              B                        ⁢            TB                    R                                    Equation        ⁢                                  ⁢                  (          1          )                    
where kB is Boltzmann constant, T is temperature, and B is the bandwidth of noise.
The resistor of the integration circuit is also the same. However, a period of time during which the Josephson junction is kept in a resistor state (more specifically, the length of time of a voltage state) is a few picoseconds, and a resistance value of the resistor is 2 to 3 O. On the other hand, because the integration resistor always generates noise, and because a resistance value is set at several mO, its noise current is large.
If thermal noise is taken into consideration, the thermal noise overlaps quantization noise in the integration circuit, and the comparator, of the modulator. Accordingly, the bit accuracy decreases. For example, if the electric power of the quantization noise is the same as that of the thermal noise, the bit accuracy decreases by 1.0 bit.
The second cause is the integration leak that exists in the integration circuit constituted of the integration resistor and the integrating inductor. This means that it is not possible to integrate a signal whose frequency is lower than the cut-off frequency fc determined by Equation (2):
                              f          c                =                  R                      2            ⁢            π            ⁢                                                  ⁢            L                                              Equation        ⁢                                  ⁢                  (          2          )                    
where R is a resistance value of the integration resistor, and L is the inductance of the integrating inductor. Because it is not possible to reduce quantization noise whose frequency is lower than or equal to this cut-off frequency in a modulator that uses an integration circuit constituted of an inductor and a resistor, the actually acquired bit accuracy is lower than a theoretical value obtained in a case where an integration circuit which is ideal for the modulator is used. For example, if a cut-off frequency is 1 MHz in the bandwidth of 10 MHz, a decrease in the bit accuracy is very little. However, if the cut-off frequency is 10 MHz, the bit accuracy decreases by 1 bit.
One of the methods for preventing the bit accuracy from being decreased by the integration leak is to reduce the cut-off frequency of the integration circuit. Accordingly, it is necessary to increase the inductance of the integration circuit, and also to decrease the resistance. However, the above measures have the following problems. First of all, the increase in inductance causes the bit accuracy to newly decrease. With the increase in inductance, the circular current to be fed back from the comparator circuit to the integration circuit decreases. In response to the decrease, the quantization spacing also decreases. Therefore, a value of the electric power of thermal noise occurring in the above-described Josephson junction becomes relatively larger in comparison with the quantization spacing. As a result, the influence of the thermal noise exerted upon the bit accuracy becomes larger, and accordingly the bit accuracy decreases.
On the other hand, if the resistance value is decreased, the input sensitivity of an analog signal and an offset current increase in the modulator. For example, if a sampling frequency is 10 GHz, the inductance is 40 pH, and the resistance is 1 mO, which are general circuit parameters of the sigma-delta modulator based on the SFQ circuit, the cut-off frequency becomes 4 MHz, the input full scale (amplitude) of an analog signal becomes 10.35 mA, and an offset current also becomes 10.35 mA. If the resistance value is decreased to one tenth so as to decrease a cut-off frequency, an input current and an offset current exceed 100 mA. Accordingly, the input sensitivity becomes worse. If an A/D converter is formed by a superconducting circuit, the compatibility between the high bit accuracy and the high sensitivity is indispensable.
In addition, in order to improve the bit accuracy of the above-described modulator based on the SFQ circuit, an increase in frequency of a sampling clock is required. However, there is also a limit in the operation speed of the SFQ circuit (more specifically, the response speed of the Josephson junction) (in the case of an existing circuit manufacturing process, about 40 GHz). For this reason, as a method for improving the bit accuracy (methods in which a frequency is increased are excluded), there are proposed a method in which a plurality of threshold values are used in the comparator circuit, and a method in which a plurality of comparators are arrayed, the comparators being driven in an interleaving manner.
The former method is based on the fact that the time at which a Josephson junction switches differs depending on the amount of a circular current of an integration circuit. The difference in time at which the Josephson junction switches is detected in a comparator circuit to acquire the comparison output, the number of bits of which is one or more. Because there is also a limit in response speed of the Josephson junction of this method, the detection of the difference in time at which the Josephson junction switches is also limited. For the present, the resolution of less than 2 bits is realistically used.
In the latter method, for example, by alternately driving two comparator circuits, the feedback whose frequency is doubled is performed for an integration circuit without increasing an operating frequency of each individual comparator circuit. As a result, a sampling frequency of the modulator as a whole is doubled in appearance. According to this method, by adding one comparator circuit to the conventional circuit, it is possible to double its frequency. In other words, it is possible to increase the bit accuracy by 1.5 times. However, the feedback signals from the two comparator circuits are merged into the integration circuit. After all, it is necessary to operate a merge circuit at doubled frequency. Under such constraint, an interleave modulating method cannot improve a sampling frequency as much as expected. As a result, the above-described two methods are influenced by the response speed of an element (in the case of the SFQ circuit, the Josephson junction) constituting the circuit.